1. Field of the Invention
The present invention relates to a substrate isolation design, and more particularly, to a substrate noise isolation design for isolating a P+ receiver from a P+ noise source.
2. Description of the Prior Art
Continuous scaling of CMOS technology has resulted in chips operating at ever-higher frequencies with analog and digital circuits residing in the same chip at ever-closer distances under realization of SOC (System On a Chip). Substrate noise coupling is an effect that no longer be ignored for SOC implementation involving circuit blocks that operate at frequencies near or above GHz level. The noise coupling via the substrate will impact the normal functioning of mixed-signal/RF circuits or digital circuits. The substrate noise can couple into signal through metal routing, device junction, or substrate. The major factors that affect the strength of this coupling are the frequency of operation, the separation distances between the circuit blocks, and the isolation schemes.
Please refer to FIG. 1 and FIG. 2. FIG. 1 and FIG. 2 are schematic diagrams of a conventional substrate structure without substrate isolation design. As shown in FIG. 1, a substrate 10 includes a P well 12, a receiver 14, a noise source 16, and a plurality of isolation structures 18 positioned on the P well 12 for preventing surface leakage currents among different devices. The substrate 10 can be a P substrate, the receiver 14 and the noise source 16 can be P+ doping regions, and the isolation structures 18 can be shallow trench isolation structures or field oxide layers.
The isolation structure 18 is formed on the surface of the P well 12 and interposed between the receiver 14 and the noise source 16, however, it is not effective in suppressing the substrate coupling effect particularly in high-frequency circuits. Industry has proposed or attempted to overcome this limitation with use of a guard ring formed around the receiver 14. A conventional guard ring is often formed by selectively placing certain dopants around the receiver 14, such as a P+ guard ring or an N well guard ring. In order to increase the reliability of the substrate isolation, multiple guard rings may be interposed between the receiver 14 and the noise source 16. Since extra photolithographic masking steps and critical mask alignment steps are required to form these guard rings, and each of which adds manufacturing time and expense as well as provides possible sources of device defects, it is desirable to provide an ideal substrate isolation design without adding masking steps.